紫光 FPGA 开发：PCIe 接口、远程升级与 AXI Bridge 接口

紫光 FPGA 开发：PCIe 接口、远程升级与 AXI Bridge 接口

PCIe DMA：AXI4-Stream 到 RAM 读写接口的转换

在项目中，PCIe DMA 负责将 AXI4-Stream 接口转换为 RAM 读写接口。支持多种模式（Gen1x1/2/4, Gen2x1/2/4），DMA Mrd/Mwr 及 1DW PIO，读写数据长度 4~4096 字节（以 DW 为单位）。

module pcie_dma (
    input wire clk,
    input wire rst,
    // AXI4-Stream input
    input wire [DATA_WIDTH - 1:0] axi4_stream_data,
    input wire axi4_stream_valid,
    output wire axi4_stream_ready,
    // RAM interface
    output reg [ADDR_WIDTH - 1:0] ram_addr,
    output reg [DATA_WIDTH - 1:0] ram_wdata,
    output reg ram_wen,
    input wire [DATA_WIDTH - 1:0] ram_rdata
);

    // 状态机定义
    typedef enum reg [2:0] {
        IDLE,
        READ_AXI4_STREAM,
        WRITE_RAM
    } state_t;

    state_t current_state, next_state;

    always @(posedge clk or posedge rst) begin
        if (rst)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (axi4_stream_valid)
                    next_state = READ_AXI4_STREAM;
            end
            READ_AXI4_STREAM: begin
                if (axi4_stream_ready)
                    next_state = WRITE_RAM;
            end
            WRITE_RAM: begin
                // 假设写完一个数据后回到 IDLE 等待下一次 AXI4-Stream 数据
                next_state = IDLE;
            end
        endcase
    end

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            ram_addr <= {ADDR_WIDTH{1'b0}};
            ram_wdata <= {DATA_WIDTH{1'b0}};
            ram_wen <= 1'b0;
            axi4_stream_ready <= 1'b0;
        end else begin
            case (current_state)
                IDLE: begin
                    axi4_stream_ready <= 1'b1;
                    ram_wen <= 1'b0;
                end
                READ_AXI4_STREAM: begin
                    ram_wdata <= axi4_stream_data;
                    axi4_stream_ready <= 1'b1;
                end
                WRITE_RAM: begin
                    ram_addr <= ram_addr + 1;
                    ram_wen <= 1'b1;
                    axi4_stream_ready <= 1'b0;
                end
            endcase
        end
    end
endmodule

代码逻辑通过状态机控制数据从 AXI4-Stream 接口到 RAM 接口的传输。在 IDLE 状态下等待 axi4_stream_valid 信号，有效则进入 READ_AXI4_STREAM 状态接收数据，完成后进入 WRITE_RAM 状态写入 RAM，写完后返回 。